FPGA

FPGA Composition

FPGA are pre-fabed silicon devices that can be programmed to any kind of digital circuit.

• Mapping
  • compare the resources specified in input synthesized netlist and checks for available resources of the target FPGA
  • divide netlist circuit into smaller blocks

• place and route

  • design fitting
  • place the blocks in the FPGA

  • routes signals between logic blocks considering timing and area constraints

    design goals

    • minimize area
    • maximize performance
    • minimize power consumption

• generate programming file

  • a bitstream file (.isc)

Programmable Logic Blocks (PLBs)

• Consists of: CLB, LAB, which implements combinational and sequential logic functions.

• programmable routing that connects these logic functions

• I/O that are connected to the logic blocks through routing interconnect - CLB: Configurable Logic Block - LAB: Logic Array Block

Configurable Logic Block (CLB)

• one or more logic element (LE) connected over an interconnect network

• each LE contains

  • a lookup table (LUT) that implements a logic function
  • a flip-flop (FF) that stores the output of the LUT
  • a multiplexer (MUX) that selects between the LUT output and the FF output

Altera FPGA

a CLB is called as LAB （Logic Array Block）

Typical Logic Element (LE)

4 input LUT based BLE (Basic Logic Element)

• LUT consists of cascaded multiplexors
• LUT inputs are select lines for internal multiplexors (MUX)
• LUT-4 uses 16 SRAM bits to implement any 4 inputs boolean function
• then it is outputted