System Verilog

language supported

1. behaviorial level (algorithm or RTL(Register transfer) level)
2. dataflow level
3. gate level (structural level)
4. switch level (transistor level)

Gate level Delays

• rise delay: from X to 1
• fall delay: from X to 0
• turn-off delay: from 1 to Z
• default time units: ps, or picosecond (10^-12 sec), default delay is 0
• it can be defined in order: #(delay_time), #(rise_time, fall_time), #(rise_time, fall_time, turn-off_time)
• it is also called transport delay, the change in input takes effect in the output after the delay time

switch level modeling

switch type	sv switch primitives
ideal MOS switch	nmos, pmos, cmos
resistive MOS switch	rnmos, rpmos, rcmos
ideal bidirectional switch	tran, tranif0, tranif1
resistive bidirectional switch	rtran, rtranif0, rtranif1
power and ground nets	supply1, supply0
pull up and pull down	pullup, pulldown

NMOS output table

in\control	0	1	x	z
0	z	0	L	L
1	z	1	H	H
x	z	x	x	x
z	z	z	z	z

PMOS output table

in\control	0	1	x	z
0	0	z	L	L
1	1	z	H	H
x	x	z	x	x
z	z	z	z	z

cMOS output table

control (n,p)	data=0	data = 1
0 , 0	0	1
0 , 1	z	z
1 , 0	0	1
1 , 1	0	1

MUX implementation

always_comb vs assign

• use always_comb with if-else or case, and more complex constructs
• use assign for delays

Behavior levelDataflow levelGate levelSwitch Level

module mux2to1 (input in[1:0], input sel, output logic out); // (1)
    always_comb begin
        if (sel == 0) out = in[0];
        else out = in[1];
    end // (2)
endmodule

1. 

2. 

module mux2to1_df(
    input in0, in1, sel,
    output logic out);
    assign out = (!sel && in0) || (sel && in1); // (1)
endmodule

1. 

module mux2to1_gate(
    input in0, in1, sel,
    output out);
    wire a0, a1, inv_sel; // define wires
    not G1(inv_sel, sel); // define NOT gate (input, output)
    and G2(a0, in0, inv_sel); // define AND gate (output, input1, input2)
    and G3(a1, in1, sel); // define AND gate (output, input1, input2)
    or #1.5 G4(out, a0, a1); // define OR gate (output, input1, input2) with 1.5 time units of delay (prevent zero-hazard)
endmodule // (1)

1. 

module mux2to1_sw(
    input in0, in1, sel,
    output out);
    wire w;
    inv G1(w,sel); //INV (out, input)
    cmos C1(out, in0, w, sel); //cmos (out, input, control p, control n)
    cmos C2(out, in1, sel, w);
endmodule // (1)

1. 

Module Implementation and Declaration

in vs, the primary block is called a module, it contains

example of a module Counter

module counter // module start declaration
# (parameter WIDTH = 4) // parameter declaration
(
    input logic clk, clear,
    output wire[WIDTH-1:0] count // (1) Primary port declaration with directions, and datatype
);
    logoc [WIDTH-1:0] cnt_val; //local variable
    always_ff @(posedge clk or posedge clear) begin //concurrent statements
        if (clear == 1) cnt_val = 0;
        else cnt_val = cnt_val + 1;

    assign count = cnt_val; // continuous assignment
endmodule // module end declaration

1. port declaration: <direction = input> <datatype = wire> <width = 1> <port name>

   where <direction> can be input, output, inout (bi-directional),

   <data type> can be logic, wire, etc. (wire is 4-state net, logic is 4-state net/variable, reg deprecated is 4-state variable),

   <width> can be 1 or n,

   eg: input logic [3:0] a, inout [3:0] b

   Note

   in sv, all module ports can be declared as logic unless multiply driven

Port Connections

there are 2 types of port connections: named and positional - named port connections: module_name instance_name(.port_name(signal_name)) - positional port connections: module_name instance_name(signal_name) - named are preferred, since you can left out ports and self documenting

suppose we have

module re_and(
    input [7:0] a,
    output y);
    assign y = &a;
endmodule

and we have top design

module top;
    wire y;
    re_and u1(.a(8'b11111111), .y(y)); // named port connections
    re_and u2(8'b11111111, y); // positional port connections
endmodule