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System Verilog

File structure

module <module_name> (
    input  logic ...,
    output logic ...
);
// internal signals
// logic, wire, etc.

// combinational logic
always_comb begin
    // ...
end

// sequential logic
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        // reset behavior
    else
        // normal operation
end

endmodule

data types

Type Description
logic Replaces reg/wire for most cases.
bit 0 or 1 only (no x or z).
byte, shortint, int, longint Signed integers of 8, 16, 32, 64 bits.
wire For purely combinational (continuous assignment) only.
reg For old style procedural assignments.

Module IO

module example (
    input  logic clk,
    input  logic rst_n,
    input  logic [3:0] in1,
    output logic [3:0] out1
);
endmodule

Combinational vs sequential Logic

Block Use For Example
always_comb Combinational logic always_comb begin out = a & b; end
always_ff Clocked (sequential) logic always_ff @(posedge clk) begin q <= d; end
always_latch Latches (rare) always_latch begin if (en) q = d; end

Example of combinational logic:

always_comb begin
    if (a > b) begin
        out = a;
    end else begin
        out = b;
    end
end

Constants

localparam int WIDTH = 16;
localparam logic [3:0] OPCODE_ADD = 4'b0010;

Operations

Operation Syntax
Addition a + b
Subtraction a - b
Bitwise AND a & b
Bitwise OR a \| b
Bitwise XOR a ^ b
Shift Left a << 2
Shift Right a >> 2
Bitwise NOT ~a

8. Memory (RAM / ROM)

Single-Port RAM Example:

module simple_ram (
    input  logic        clk,
    input  logic        we,
    input  logic [7:0]  addr,
    input  logic [15:0] din,
    output logic [15:0] dout
);
    logic [15:0] mem [0:255];

    always_ff @(posedge clk) begin
        if (we)
            mem[addr] <= din;
        dout <= mem[addr];
    end
endmodule

ROM Initialization:

initial begin
    mem[0] = 16'h0001;
    mem[1] = 16'hABCD;
end

9. Multiplexer Example

assign out = sel ? a : b;

or

always_comb begin
    if (sel)
        out = a;
    else
        out = b;
end

10. Testbench Essentials

Purpose Example
Module Instantiation module tb; dut uut (...); endmodule
Clock Generation always #5 clk = ~clk;
Reset Generation initial begin rst_n = 0; #10 rst_n = 1; end
Input Stimulus initial begin a = 1; #10 a = 0; end
Simulation End initial begin #100 $finish; end

11. Assertions (Optional, for advanced validation)

assert property ( @(posedge clk) (req |-> ##[1:3] ack) )
    else $error("ACK did not follow REQ in 1-3 cycles");
Entity Convention
Modules snake_case, e.g., alu_core
Ports snake_case, e.g., data_in, addr_out
Internal Signals logic, prefix by purpose, e.g., alu_result

🏁 Tips for Your Project

  • Start simple: Implement PC + Instruction Memory first.
  • Use parameterized opcodes: Easier to change later.
  • Write unit testbenches: For ALU, PC, Register File separately.
  • Use meaningful initial values in RAM/ROM for easier debug.

Would you also like me to generate a quick one-page printable markdown table version for easy copy-paste into your docs folder? (Useful if you want to keep it inside your project repo.) 📑