basic structure of a System Verilog file

module <module_name> (
    input  logic ...,
    output logic ...
);
// internal signals
// logic, wire, etc.
logic [31:0] internal_signal;
// combinational logic
always_comb begin
    internal_signal = input_signal1 & input_signal2;
end
// sequential logic
always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        internal_signal <= 32'b0; // reset behavior
    else
        internal_signal <= internal_signal + 1; // normal operation
end
endmodule

keywords and Syntax

Keyword	Description
`module`	Defines a module.
`endmodule`	Ends a module definition.
`input`	Declares input ports.
`output`	Declares output ports.
`logic`	Declares a logic type variable.
`always_comb`	Block for combinational logic.
`always_ff`	Block for sequential (clocked) logic.
`if`, `else`	Conditional statements.
`posedge`	Trigger on the rising edge of a clock.
`negedge`	Trigger on the falling edge of a signal.
`<=`	Non-blocking assignment (used in sequential logic).
`=`	Blocking assignment (used in combinational logic).
`begin`, `end`	Define a block of code.
`wire`	Declares a wire type variable (for continuous assignment).
`reg`	Declares a reg type variable (for procedural assignments).
`initial`	Block that runs once at the start of simulation.

Buildin functions

Function	Description
`$display(text)`	Prints text to the console during simulation.
`$finish()`	Ends the simulation.
`$stop()`	Pauses the simulation.
`$random`	Generates a random number.
`$time`	Returns the current simulation time.
`$clog2(value)`	Returns the ceiling of the base-2 logarithm of value.
`$signed(value)`	Casts value to a signed type.
`$unsigned(value)`	Casts value to an unsigned type.
`$itor(value)`	Converts an integer to a real number.
`$rtoi(value)`	Converts a real number to an integer.
`$fopen("filename")`	Opens a file and returns a file descriptor.
`$fclose(file_descriptor)`	Closes a file given its descriptor.
`$fwrite(file_descriptor, text)`	Writes text to a file given its descriptor.
`$readmemh("filename", memory_array)`	Reads hexadecimal data from a file into a memory array.
`$readmemb("filename", memory_array)`	Reads binary data from a file into a memory array.

operators

Operator	Description
`#number`	delay assignment by number time units, eg: `assign #10 a = b;`
`+`	Addition
`-`	Subtraction
`*`	Multiplication
`/`	Division
`%`	Modulus
`&`	Bitwise AND
`\\|`	Bitwise OR
`^`	Bitwise XOR
`~`	Bitwise NOT
`<<`	Shift Left
`>>`	Shift Right
`==`	Equality
`!=`	Inequality
`<`	Less Than
`>`	Greater Than
`<=`	Less Than or Equal To
`>=`	Greater Than or Equal To
`&&`	Logical AND
`\\|\\|`	Logical OR
`!`	Logical NOT
`? :`	Ternary Conditional Operator
`<=`	Non-blocking Assignment
`=`	Blocking Assignment

data types

Type	Description
`logic`	Replaces `reg`/`wire` for most cases.
`bit`	0 or 1 only (no `x` or `z`).
`byte`, `shortint`, `int`, `longint`	Signed integers of 8, 16, 32, 64 bits.
`wire`	For purely combinational (continuous assignment) only.
`reg`	For old style procedural assignments.
`real`, `shortreal`	Floating point numbers.
`time`	Special type for simulation time values.
`realtime`	Special type for real time values.

Parameters

Parameters allow you to define constants within a module that can be modified at compile time or during instantiation. This is useful for creating configurable modules.

Basic Parameter Declaration

module adder #(
    parameter WIDTH = 8 // Default width of the adder
) (
    input  logic [WIDTH-1:0] a, b,
    output logic [WIDTH-1:0] sum
);
    assign sum = a + b;
endmodule

Using `defparam` (Not Recommended for New Designs)

defparam is an older method to modify parameters, and its use is generally discouraged in favor of more modern approaches.

module top;
    adder #(.WIDTH(16)) adder_instance ();
endmodule

Parameter Override during Module Instantiation

This is the preferred way to modify parameters.

module top;
    adder #(
        .WIDTH(16) // Override the WIDTH parameter to 16
    ) adder_instance (
        .a(input_a),
        .b(input_b),
        .sum(output_sum)
    );
endmodule

Using `set_param` (Tool-Specific)

set_param is a tool-specific command used in simulation or synthesis environments to override parameter values. It's not part of the SystemVerilog language itself but is supported by many EDA tools. Consult your tool's documentation for the exact syntax. A general example might look like this in a tool command script:

set_param top.adder_instance.WIDTH 32

This command would set the WIDTH parameter of the adder_instance within the top module to 32. This is often used for testbench configurations or during synthesis to explore different design options without modifying the source code.

Modifying Parameters in Testbenches

Parameters can be modified in testbenches to test different configurations of a module.

module testbench;
    logic [7:0] a, b;
    logic [7:0] sum;

    // Instantiate the module with default parameter
    adder adder_instance (a, b, sum);

    initial begin
        // Test with default width
        a = 8'h01;
        b = 8'h02;
        #10;
        $display("Sum with default width: %h", sum);

        // Test with overridden width (using a different instance)
        adder #( .WIDTH(16) ) adder_instance_16 (a, b, sum);
        a = 16'h0001;
        b = 16'h0002;
        #10;
        $display("Sum with overridden width: %h", sum);

        $finish;
    end
endmodule