SHA-256 Hardware Simulator

Pure JavaScript implementation using bitwise operations to simulate logic gates (ROTR, SHR, XOR, AND). Designed for easy translation to Verilog/VHDL.

Input Message

Simulates 32-bit register operations

Registers & Output

Final SHA-256 Hash (Hex)

Waiting for input...

Convert input to Bytes (Hex)

Binary Padding Simulation

Initial Hash Values (H0-H7)

0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a,
0x510e527f, 0x9b05688c, 0x1f83d9ab, 0x5be0cd19

Round Constants (K0-K63)

0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5...
(64 32-bit constants derived from cube roots of primes)